Build a Racket based RISC-V assembler

Documentation

Registers

The RISC-V RV32 has 32 32bit registers.

#lang racket
(define-struct register (name width code))

(define zero (make-register 'zero 32 0))
...

Risc-V

• Webbased Risc-V Simulator
• RISC-V can be fun if they don't mess it up
• RISC-V simulator rv8
• VexRiscv CPU is an fpga friendly RISC-V ISA CPU implementation

More Racket based assemblers

• Asi64
• Beautiful Racket
• Brag a better Racket AST generator
• IA32 Assembler